74AVC2T45

Wide supply voltage range:
` V<sub>CC(A)</sub>: 0.8 V to 3.6 V
` V_CC(B): 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
` JESD8-12 (0.8 V to 1.3 V)
` JESD8-11 (0.9 V to 1.65 V)
` JESD8-7 (1.2 V to 1.95 V)
` JESD8-5 (1.8 V to 2.7 V)
` JESD8-B (2.7 V to 3.6 V)
ESD protection:
` HBM JESD22-A114E Class 3B exceeds 8000 V
` MM JESD22-A115-A exceeds 200 V
` CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
` 500 Mbps (1.8 V to 3.3 V translation)
` 320 Mbps (< 1.8 V to 3.3 V translation)
` 320 Mbps (translate to 2.5 V or 1.8 V)
` 280 Mbps (translate to 1.5 V)
` 240 Mbps (translate to 1.2 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
IOFF circuitry provides partial Power-down mode operation
SOT765-1 and SOT833-1 package options
Specified from -40 to +85 and -40 to +125

[1] The minimum input voltage rating and output voltage ratings may be exceeded if the input and output current  atings are observed.
[2] V_CCO is the supply voltage associated with the output port.
[3] V_CCO + 0.5 V should not exceed 4.6 V.
[4] For VSSOP8 package: above 110 the value of P_tot derates linearly with 8 mW/K.
For XSON8 package: above 45 the value of P_tot derates linearly with 2.4 mW/K.

The 74AVC2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V_CC(A) and V_CC(B)). Both V_CC(A) and V_CC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR of the 74AVC2T45 are referenced to V_CC(A) and pins nB are referenced to V_CC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.

The 74AVC2T45 is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at GND level, both A and B are in the high-impedance OFF-state.