74FCT273T

•Std., A, and C speed grades
•Low input and output leakage £1mA (max.)
•CMOS power levels
•True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.)
•High drive outputs (-15mA IOH, 48mA IOL)
•Meets or exceeds JEDEC standard 18 specifications
•Product available in Radiation Tolerant and Radiation Enhanced versions
•Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked)
•Available in DIP, SOIC, QSOP, CERPACK and LCC packages

The 74FCT273T is octal D flip-flops built using an advanced dual metal CMOS technology. The 74FCT273T has eight edge-triggered D-type flipflops with individual D inputs and O outputs. The common buffered Clock (CP) and Master Reset (MR ) inputs load and reset (clear) all flip-flops simultaneously.

The register of the 74FCT273T is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's O output.

All outputs of the 74FCT273T will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR  input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.