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74FR74SC

Features: · 74FR74 is pin-for-pin compatible with the 74F74· True 150 MHz fMAX capability on 74FR74· Outputs sink 24 mA and source 24 mA· Guaranteed pin-to-pin skew specificationsPinoutSpecificationsStorage Temperature .......................................−65°C to +150°CAmbient Temperature...

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SeekIC No. : 004250625 Detail

74FR74SC: Features: · 74FR74 is pin-for-pin compatible with the 74F74· True 150 MHz fMAX capability on 74FR74· Outputs sink 24 mA and source 24 mA· Guaranteed pin-to-pin skew specificationsPinoutSpecification...

74FR74SC Data Sheet

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Part Number:
74FR74SC
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·  74FR74 is pin-for-pin compatible with the 74F74
·  True 150 MHz fMAX capability on 74FR74
·  Outputs sink 24 mA and source 24 mA
·  Guaranteed pin-to-pin skew specifications


Pinout

Connection Diagram


Specifications

Storage Temperature .......................................−65°C to +150°C
Ambient Temperature under Bias .....................−55°C to +125°C
Junction Temperature under Bias...................... −55°C to +150°C
VCC Pin Potential to Gr.ound Pin ...........................−0.5V to +7.0V
Input Voltage (Note 2) ..........................................−0.5V to +7.0V
Input Current (Note 2) ....................................−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output .......................................................−0.5V to VCC
Current Applied to Output
in LOW State (Max).................................. twice the rated IOL (mA)
ESD Last Passing Voltage (Min)............................................ 2000V


Description

The 74FR74SC is dual D-type flip-flops with true and complement (Q/Q) outputs. On the 74FR74, data at the D inputs is transferred to the outputs on the rising edge of the clock input (CPn). The 74FR74SC is the negative edge triggered version of this device. Both parts feature asynchronous clear (CDn) and set (SDn) inputs which are low level enabled.




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