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MFG:ST Package Cooled:SOP
Part Number: 74HC137
MFG: ST
Package Cooled: SOP
Description: The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL)....
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74HC137
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DataSheet
General Description
74HC137 General Description
The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A.
The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LEremains HIGH.
The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.
The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems.
74HC137 Features
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active LOW mutually exclusive outputs
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from -40 °C to +80 °C and from -40 °C to +125 °C.
Multiple input enable for easy expansion or independent controls
Active LOW mutually exclusive outputs
Low-power dissipation
Complies with JEDEC standard no. 7A
ESD protection:
- HBM EIA/JESD22-A114-B exceeds 2000 V
- MM EIA/JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from -40 °C to +80 °C and from -40 °C to +125 °C.
74HC137 Connection Diagram
74HC137
PDF/DataSheet Download
- Datasheet: 74HC137
- File Size: 110184 KB
- Manufacturer: PHILIPS [Philips Semiconductors]
- Click here to Download
- ·74H00
- ETC [ETC]
- QUAD 2-INPUT NAND GATE
- 62068 KB
- ·74H00DC
- ETC [ETC]
- QUAD 2-INPUT NAND GATE
- 62068 KB
- ·74H00FC
- ETC [ETC]
- QUAD 2-INPUT NAND GATE
- 62068 KB
- ·74H00PC
- ETC [ETC]
- QUAD 2-INPUT NAND GATE
- 62068 KB
- ·74H11
- ETC [ETC]
- TRIPLE 3-INPUT AND GATE
- 57988 KB
- ·74H11DC
- ETC [ETC]
- TRIPLE 3-INPUT AND GATE
- 57988 KB
- ·74H11FC
- ETC [ETC]
- TRIPLE 3-INPUT AND GATE
- 57988 KB
- ·74H11PC
- ETC [ETC]
- TRIPLE 3-INPUT AND GATE
- 57988 KB
74HC137 Relative Products
74HC133
The 74HC133 is an high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC133 provides the 13-input NAND function.
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