74HC3G06

Features: · Wide supply voltage range from 2.0 to 6.0 V· Symmetrical output impedance· High noise immunity· Low power dissipation· ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A115-A exceeds 200 V.· Balanced propagation delays· Very small 8 pins package.PinoutSpecifications ...

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74HC3G06 Picture
SeekIC No. : 004250755 Detail

74HC3G06: Features: · Wide supply voltage range from 2.0 to 6.0 V· Symmetrical output impedance· High noise immunity· Low power dissipation· ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 VMM EIA/JESD22-A...

floor Price/Ceiling Price

Part Number:
74HC3G06
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Description



Features:

· Wide supply voltage range from 2.0 to 6.0 V
· Symmetrical output impedance
· High noise immunity
· Low power dissipation
· ESD protection:
    HBM EIA/JESD22-A114-A exceeds 2000 V
    MM EIA/JESD22-A115-A exceeds 200 V.
· Balanced propagation delays
· Very small 8 pins package.



Pinout

  Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage   -0.5 +7.0 V
IIK input diode current VI < -0.5 V or VI > VCC + 0.5 V; note 1 - ±20 mA
IOK output diode current VO < -0.5 V; note 1 - -20 mA
VO output voltage active mode; note 1 -0.5 VCC + 0.5 V
high-impedance mode; note 1 -0.5 7.0 V
IO output sink current -0.5 V < VO < 7.0 V; note 1 - -25 mA
ICC, IGND VCC or GND current note 1 - 50 mA
Tstg storage temperature   -65 +150 °C
PD power dissipation Tamb = -40 to +125 °C; note 2 - 300 mW



Description

The 74HC3G06/74HCT3G06 is a high-speed Si-gate CMOS device. Specified in compliance with JEDEC standard no. 7A.

The 74HC3G06/74HCT3G06 provides three inverting buffers.

The outputs of the 74HC3G06; 74HCT3G06 devices are open drains and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. For digital operation this device must have a pull-up resistor to establish a logic HIGH-level.




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