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MFG:ST Package Cooled:SMD
Part Number: 74HC4050
MFG: ST
Package Cooled: SMD
Description: The 74HC4050 is a high-speed Si-gate CMOS device and is pin compatible with the "4050" of the "4000B" ...
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74HC4050
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DataSheet
General Description
74HC4050 General Description
The 74HC4050 is a high-speed Si-gate CMOS device and is pin compatible with the "4050" of the "4000B" series. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4050 provides six non-inverting buffers with a modified input protection structure, which has no diode connected to VCC. Input voltages of up to 15 V may therefore be used. This feature enables the non-inverting buffers to be used as logic level translators, which will convert high level logic to low level logic, while operating from a low voltage power supply. For example 15 V logic ("4000B series") can be converted down to 2 V logic.
The actual input switch level remains related to the VCC and is the same as mentioned in the family characteristics.
74HC4050 Features
· Output capability: standard
· ICC category: SSI
· ICC category: SSI
74HC4050 Typical Application
` Converting 15 V logic ("4000B" series) down to 2 V logic.
74HC4050 Connection Diagram
74HC4050D
PDF/DataSheet Download
- Datasheet: 74HC4050D
- File Size: 45467 KB
- Manufacturer: PHILIPS [Philips Semiconductors]
- Click here to Download
- ·74H00
- ETC [ETC]
- QUAD 2-INPUT NAND GATE
- 62068 KB
- ·74H00DC
- ETC [ETC]
- QUAD 2-INPUT NAND GATE
- 62068 KB
- ·74H00FC
- ETC [ETC]
- QUAD 2-INPUT NAND GATE
- 62068 KB
- ·74H00PC
- ETC [ETC]
- QUAD 2-INPUT NAND GATE
- 62068 KB
- ·74H11
- ETC [ETC]
- TRIPLE 3-INPUT AND GATE
- 57988 KB
- ·74H11DC
- ETC [ETC]
- TRIPLE 3-INPUT AND GATE
- 57988 KB
- ·74H11FC
- ETC [ETC]
- TRIPLE 3-INPUT AND GATE
- 57988 KB
- ·74H11PC
- ETC [ETC]
- TRIPLE 3-INPUT AND GATE
- 57988 KB
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74HC4049
The 74HC4049 is a high-speed Si-gate CMOS device andis pin compatible with the "4049" of the "4000B" series.is specified in compliance with JEDEC standard no. 7A.The 74HC4049 provides six inverting buffers with amodified input protection structure, which has...
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