74HC93

The 74HC93 is designed as high-speed si-gate CMOS devices and are pin compatible with low power schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. It is 4-bit binary ripple counters. The devices consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the high-to-low clock transition.

It has four features. The first one is various counting modes. The second one is asynchronous master reset. The third one its output capability is standard. The fourth one is its ICC category is MSI. That are all the main features.

Some important AC characteristics and specifications have been concluded into several points as follow.For Tamb=25°C the first one is about its propagation delay CP0 to Q0 which would be typ 41ns and max 125ns at Vcc=2.0V and would be typ 15ns and max 25ns at Vcc=4.5V and would be typ 12ns and max 21ns at Vcc=6.0V. The second one is about its propagation delay CP1 to Q1 which would be typ 49ns and max 135ns at Vcc=2.0V and typ 16ns and max 27ns at Vcc=4.5V and would be typ 13ns and max 23ns at Vcc=6.0V. The third one is about its propagation delay CP1 to Q2 which would be typ 61ns and max 185ns at Vcc=2.0V and typ 22ns and max 37ns at Vcc=4.5V and would be typ 18ns and max 31ns at Vcc=6.0V. The fourth one is about its propagation delay CP1 to Q3 which would be typ 80ns and max 245ns at Vcc=2.0V and typ 29ns and max 49ns at Vcc=4.5V and would be typ 23ns and max 42ns at Vcc=6.0V. The fifth one is about its output transition time which would be typ 19ns and max 75ns at Vcc=2.0V and typ 7ns and max 15ns at Vcc=4.5V and would be typ 6ns and max 13ns at Vcc=6.0V. And so on. For more information please contact us for details.