74HCT4020

The 74HCT4020 is high-speed Si-gate CMOS devices and are pin compatible with the "4020" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A.

The 74HCT4020 is 14-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q₀, Q3 to Q₁₃).

The counter of the 74HCT4020 is advanced on the HIGH-to-LOW transition of CP.
 
A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP.

Each counter stage of the 74HCT4020 is a static toggle flip-flop.