74LCX74

 · 5VTOLERANT INPUTS
 · HIGHSPEED:
    f_MAX = 150MHz(MAX.) atV_CC= 3V
 · POWER-DOWNPROTECTIONON INPUTS ANDOUTPUTS
 · SYMMETRICAL OUTPUT IMPEDANCE:
    |IOH| = I_OL = 24mA (MIN)
 · PCI BUSLEVELSGUARANTEED AT 24mA
 · BALANCEDPROPAGATIONDELAYS:
    t_PLH t_PHL
 · OPERATINGVOLTAGERANGE:
    V_CC (OPR)= 2.0Vto 3.6V (1.5VData Retention)
 · PINANDFUNCTION COMPATIBLEWITH
     74 SERIES74
 · LATCH-UPPERFORMANCE EXCEEDS500mA
 · ESDPERFORMANCE:
     HBM>2000V;MM> 200V

The 74LCX74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESETAND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C²MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs.

A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse.

CLEAR and PRESET of the 74LCX74 are independent of the clock and accomplished by a low setting on the appropriate input.

It has same speed performance of the 74LCX74 at 3.3V than 5V,AC/ACT family, combined with a lower power consumption.

All inputs and outputs of the 74LCX74 are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.