74LCXH162244

Features:

`5V tolerant control inputs and outputs
`2.3V3.6V VCC specifications provided
`Outputs include equivalent series resistance of 26 to
`make external termination resistors unnecessary and reduce overshoot and undershoot
`Bushold on data inputs eliminates the need for external
`pull-up/pull-down resistors
`5.3 ns tPD max (VCC = 3.0V), 20 µA ICC max
`Power down high impedance inputs and outputs
`±12 mA output drive (VCC = 3.0V)
`Implements patented noise/EMI reduction circuitry
`Latch-up performance exceeds 500 mA
`ESD performance:Human body model > 2000V Machine model > 200V


Pinout




Specifications

Symbol	Parameter		Value	Conditions	Units
VCC	Supply Voltage		−0.5 to +7.0		V
VI	DC Input Voltage	OE	−0.5 to +7.0		V
		I0 - I15	−0.5 to VCC + 0.5
VO	DC Output Voltage		−0.5 to +7.0 −0.5 to VCC + 0.5	Output in 3-STATE Output in HIGH or LOW State (Note 2)	V
IIK	DC Input Diode Current		−50	VI < GND	mA
IOK	DC Output Diode Current		−50 +50	VO < GND VO > VCC	mA
IO	DC Output Source/Sink Current		±50		mA
ICC	DC Supply Current per Supply Pin		±100		mA
IGND	DC Ground Current per Ground Pin		±100		mA
TSTG	Storage Temperature		−65 to +150		mA

Description

The 74LCXH162244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.

The 74LCXH162244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. In addition, the outputs include equivalent 26Ω (nominal) series resistors to reduce overshoot and undershoot and are designed to sink/source up to 12 mA at VCC = 3.0V.

The 74LCXH162244 is designed for low voltage (2.5V or3.3V) VCC applications with capability of interfacing to a 5V signal environment.

The 74LCXH162244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.