MFG:MIT Package Cooled:DIP D/C:07+
MFG: MIT
Package Cooled: DIP
D/C: 07+
Description: The SN54/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. The...
The SN54/74LS114A offers common clock and common clear inputs and individual J, K, and set inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.
| Symbol | Parameter | Min | Typ | Max | Unit | |
| VCC | Supply Voltage | 54 74 |
4.5 4.75 |
5.0 5.0 |
5.5 5.25 |
V |
| TA | Operating Ambient Temperature Range | 54 74 |
55 0 |
25 25 |
125 70 |
°C |
| IOH | Output Current - High | 54,74 | -0.4 | mA | ||
| IOL | Output Current - Low | 54 74 |
4.0 8.0 |
mA |
74L71
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The SN54/74LS113A offers individual J, K, set, and clock inputs. These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change ...
The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to ...
The 74LS109A consists of two high speed completely independent transition clocked JK flip-flops. The clocking operation is independent of riseand fall times of the clock waveform. The JK design allows operation as a D flip-flop by simply connecting the J and...
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