74LV164

Features: • Optimized for Low Voltage applications: 1.0 to 3.6V• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V• Typical VOLP (output ground bounce) < 0.8V @ VCC = 3.3V, Tamb = 25°C• Typical VOHV (output VOH undershoot) > 2V @ VCC = 3.3V, Tamb = 25°C• I...

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SeekIC No. : 004251145 Detail

74LV164: Features: • Optimized for Low Voltage applications: 1.0 to 3.6V• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V• Typical VOLP (output ground bounce) < 0.8V @ VCC = 3.3V...

floor Price/Ceiling Price

Part Number:
74LV164
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

• Optimized for Low Voltage applications: 1.0 to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical VOLP (output ground bounce) < 0.8V @ VCC = 3.3V, Tamb = 25°C
• Typical VOHV (output VOH undershoot) >  2V @ VCC = 3.3V, Tamb = 25°C
• Ideal for addressable register applications
• Data enable for address and data synchronization applications
• Eight positive-edge triggered D-type flip-flops
• Output capability: standard



Pinout

  Connection Diagram


Specifications

In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +7.0 V
±IIK DC input diode current VI < 0.5 or VI > VCC + 0.5V 20 mA
±IOK DC output diode current VO < 0.5 or VO > VCC + 0.5V 50 mA
±IO DC output source or sink current
standard outputs
0.5V < VO < VCC + 0.5V 25 mA
±IGND,
±ICC
DC VCC or GND current for types with
standard outputs
  50
mA
Tstg Storage temperature range   65 to +150 °C
PTOT Power dissipation per package
plastic DIL
plastic mini-pack (SO)
plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: 40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mW


NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.




Description

The 74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT164.

The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (Dsa or Dsb); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q0, which is the logical AND of the two data inputs (Dsa, Dsb) that existed one set-up time prior to the rising clock edge.

A LOW on the master reset (MR) of the 74LV164 input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.




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