74LV165A

Features: · Wide supply voltage range from 2.0 to 5.5 V· Complies with JEDEC standard: JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V) JESD8-1A (4.5 to 5.5 V).· 5.5 V tolerant inputs/outputs· CMOS LOW power consumption· Direct interface with TTL levels (2.7 to 3.6 V)· Power-down mode· Asynchro...

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SeekIC No. : 004251147 Detail

74LV165A: Features: · Wide supply voltage range from 2.0 to 5.5 V· Complies with JEDEC standard: JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V) JESD8-1A (4.5 to 5.5 V).· 5.5 V tolerant inputs/outputs· CM...

floor Price/Ceiling Price

Part Number:
74LV165A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

· Wide supply voltage range from 2.0 to 5.5 V
· Complies with JEDEC standard:
    JESD8-5 (2.3 to 2.7 V)
    JESD8B/JESD36 (2.7 to 3.6 V)
    JESD8-1A (4.5 to 5.5 V).
· 5.5 V tolerant inputs/outputs
· CMOS LOW power consumption
· Direct interface with TTL levels (2.7 to 3.6 V)
· Power-down mode
· Asynchronous 8-bit parallel load
· Synchronous serial input
· Latch-up performance exceeds 250 mA
· ESD protection:
    HBM EIA/JESD22-A114-A exceeds 2000 V
    MM EIA/JESD22-A115-A exceeds 200 V.



Pinout

  Connection Diagram


Description

The 74LV165A is a high-performance, low-power,low-voltage, Is-gate CMOS device and superior to mostadvanced CMOS compatible TTL families.Schmitt-trigger action at all inputs makes the circuittolerant for slower input rise and fall times.
This device is fully specified for partial-power-downapplications using Ioff. The Ioff circuitry disables the output, preventing the damaging current back flow through thedevice when it is powered down.
The 74LV165A is an 8-bit parallel-load or serial-in shiftregister with complementary serial outputs (Q7 and Q7available from the last stage. When the parallel-load input(PL) is LOW, parallel data from the inputs D0 to D7 areloaded into the register asynchronously. When input PL isHIGH, data enters the register serially at the input DS andshifts one place to the right (Q0®Q1®Q2, etc.) with eachpositive-going clock transition. This feature allowsparallel-to-serial converter expansion by tying the outputQ7 to the input DS of the succeeding stage.
The clock input of the 74LV165A is a gate-OR structure which allows oneinput to be used as an active LOW clock enable input (CE)
input. The pin assignment of the 74LV165A for the inputs CP and CE isarbitrary and can be reversed for layout convenience. TheLOW-to-HIGH transition of the input CE should only takeplace while CP HIGH for predictable operation.




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