74LVC2G240

Features:

` Wide supply voltage range from 1.65 to 5.5 V
` 5 V tolerant input/output for interfacing with 5 V logic
` High noise immunity
` Complies with JEDEC standard:
  JESD8-7 (1.65 to 1.95 V)
  JESD8-5 (2.3 to 2.7 V)
  JESD8B/JESD36 (2.7 to 3.6 V).
` ±24 mA output drive (V<sub>CC</sub> = 3.0 V)
` CMOS low power consumption
` Latch-up performance exceeds 250 mA
` Direct interface with TTL levels
` Inputs accept voltages up to 5 V
` ESD protection:
  HBM EIA/JESD22-A114-A exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V.
` Specified from -40 to +85 °C and -40 to +125 °C.


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCC	supply voltage		-0.5	+6.5	V
IIK	input diode current	VI< 0	-	-50	mA
VI	input voltage	note 1	-0.5	+6.5	V
IOK	output diode current	VO> VCC or VO< 0	-	±50	mA
VO	output voltage	enable mode; notes 1 and 2	-0.5	VCC + 0.5	V
		disable mode; notes 1 and 2	-0.5	+6.5	V
		Power-down mode; notes 1 and 2	-0.5	+6.5	V
IO	output source or sink current	VO = 0 to VCC	-	±50	mA
ICC, IGND	VCC or GND current		-	±100	mA
Tstg	storage temperature		-65	+150	°C
PD	power dissipation	Tamb = -40 °C to +125 °C; note 3	-	300	mW

Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. When V_CC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
3. Above 110 °C the value of P_D derates linearly with 8 mW/K.


Description

The 74LVC2G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 and 5 V environment.

The 74LVC2G240 is fully specified for partial power-down applications using I_off. The I_off circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74LVC2G240 is a dual inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A HIGH level at pins nOE causes outputs to assume a high-impedance OFF-state. Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise and fall times.