74LVC373A

PinoutSpecifications SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage 0.5 to +6.5 V IIK DC input diode current VI0 50 mA VI DC input voltage Note 2 0.5 to +6.5 V IOK DC output diode current VOVCC or VO 0 ±50 mA VO DC output voltage; output HIG...

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SeekIC No. : 004251342 Detail

74LVC373A: PinoutSpecifications SYMBOL PARAMETER CONDITIONS RATING UNIT VCC DC supply voltage 0.5 to +6.5 V IIK DC input diode current VI0 50 mA VI DC input voltage Note 2 0.5 to ...

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Part Number:
74LVC373A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/2

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Product Details

Description



Pinout

  Connection Diagram


Specifications

SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage   0.5 to +6.5 V
IIK DC input diode current VI0 50 mA
VI DC input voltage Note 2 0.5 to +6.5 V
IOK DC output diode current VOVCC or VO 0 ±50 mA
VO DC output voltage; output HIGH or LOW state Note 2 0.5 to VCC +0.5 V
DC output voltage; output 3-State Note 2 0.5 to 6.5
IO DC output source or sink current VO = 0 to VCC ±50 mA
IGND,ICC DC VCC or GND current   ±100 mA
Tstg Storage temperature range   65 to +150
PTOT

Power dissipation per package

plastic mini-pack (SO)

plastic shrink mini-pack (SSOP and TSSOP)

above +70°C derate linearly with8mW/K

above +60°C deratelinearlywith5.5mW/K

500

500

mW



Description

The 74LVC373A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.

The 74LVC373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE ) input are common to all internal latches.

The '373' consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one setup time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE  input does not affect the state of the latches.

The '373' is functionally identical to the '573', but the '573' has a different pin arrangement.




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