74LVC3G04

Features:

Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
  JESD8-7 (1.65 V to 1.95 V)
  JESD8-5 (2.3 V to 2.7 V)
  JESD8-B/JESD36 (2.7 V to 3.6 V).
ESD protection:
  HBM EIA/JESD22-A114-B exceeds 2000 V
  MM EIA/JESD22-A115-A exceeds 200 V.
±24 mA output drive (V_CC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
SOT505-2 and SOT765-1 package
Specified from -40 °C to +85 °C and -40 °C to +125 °C.


Pinout




Specifications

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCC	supply voltage		-0.5	+6.5	V
IIK	input diode current	VI< 0	-	-50	mA
VI	input voltage	[1]	-0.5	+6.5	V
IOK	output diode current	VO< 0 V	-	±50	mA
VO	output voltage	active mode [1] [2]	-0.5	VCC + 0.5	V
		Power-down mode[1] [2]	-0.5	+6.5	V
IO	output source or sink current	VO = 0 V to VCC	-	±50	mA
ICC, IGND	VCC or GND current		-	±100	mA
Tstg	storage temperature		-65	+150	°C
Ptot	power dissipation	Tamb = -40 °C to +125 °C	-	300	mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When V_CC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.


Description

The 74LVC3G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

The 74LVC3G04 is fully specified for partial power-down applications using I_off. The I_off circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

The 74LVC3G04 provides three inverting buffers.