74LVT573D

Number of Circuits : 8
Minimum Operating Temperature : - 40 C
Polarity : Non-Inverting
Maximum Operating Temperature : + 85 C
Number of Output Lines : 8
Low Level Output Current : 32 mA
Packaging : Tube
Package / Case : SO-20
Supply Voltage - Max : 3.6 V
High Level Output Current : - 32 mA
Logic Type : TTL
Supply Voltage - Min : 2.7 V
Logic Family : LVT
Propagation Delay Time : 2.7 ns at 3.3 V


Description

The 74LVT573D belongs to LVT573 family which is a high-performance BiCMOS product designed for VCC operation at 3.3V. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.

The features of 74LVT573D can be summarized as (1)inputs and outputs on opposite side of package allow easy interface to microprocessors; (2)3-state output buffers; (3)common output enable; (4)TTL input and output switching levels; (5)input and output interface capability to systems at 5V supply; (6)bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs; (7)live insertion/extraction permitted; (8)no bus current loading when output is tied to 5V bus; (9)latch-up protection exceeds 500mA per JEDEC Std 17; (10)power-up 3-state; (11)power-up reset; (12)ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per machine model.

The absolute maximum ratings of 74LVT573D are (1)VCC DC supply voltage: -0.5 to +4.6 V; (2)IIK DC input diode current (VI < 0): -50 mA; (3)VI DC input voltage3: -0.5 to +7.0 V; (4)IOK DC output diode current(VO < 0): -50 mA; (5)VOUT DC output voltage3(output in off or high state): -0.5 to +7.0V; (6)IOUT DC output current(output in low state/output in high state): 128/-64mA; (7)Tstg storage temperature range: -65 to 150 °C.(1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings of the 74LVT573D may be exceeded if the input and output clamp current ratings are observed.).