74LVX20

Features:

HIGH SPEED : tPD = 5.5ns (TYP.) at V_CC = 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL : V_IL=0.8V, VI_H=2V at V_CC=3V
LOW POWER DISSIPATION: I_CC = 2 mA (MAX.) at T_A=25°C
LOW NOISE: V_OLP = 0.3V (TYP.) at V_CC = 3.3V
SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)
    VBALANCED PROPAGATION DELAYS: tPLH @ tPHL
OPERATING VOLTAGE RANGE: V_CC(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS 


Pinout




Specifications

Symbol	Parameter	Value	Unit
VCC	Supply Voltage	-0.5 to +7.0	V
VI	DC Input Voltage	-0.5 to +7.0	V
VO	DC Output Voltage	-0.5 to VCC + 0.5	V
IIK	DC Input Diode Current	-20	mA
IOK	DC Output Diode Current	± 20	mA
IO	DC Output Current	± 25	mA
ICC or IGND	DC VCC or Ground Current	± 50	mA
Tstg	Storage Temperature	-65 to +150	°C
TL	Lead Temperature (10 sec)	300	°C

Description

The 74LVX20 is a low voltage CMOS DUAL 4-INPUT NAND GATE fabricated with sub-micron 2 silicon gate and double-layer metal wiring C MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.

The internal circuit of the 74LVX20 is composed of 3 stages including buffer output, which provides high noise immunity and stable output. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.  This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.