74LVX238

Features: HIGH SPEED : tPD = 5.5ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3VLOW POWER DISSIPATION: ICC = 2 mA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) VBALANCED PROPAGATION DEL...

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SeekIC No. : 004251612 Detail

74LVX238: Features: HIGH SPEED : tPD = 5.5ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3VLOW POWER DISSIPATION: ICC = 2 mA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V ...

floor Price/Ceiling Price

Part Number:
74LVX238
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/29

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Product Details

Description



Features:

 HIGH SPEED : tPD = 5.5ns (TYP.) at VCC = 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V
LOW POWER DISSIPATION: ICC = 2 mA (MAX.) at TA=25°C
LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V
SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)
    VBALANCED PROPAGATION DELAYS: tPLH @ tPHL
OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7.0 V
VI DC Input Voltage -0.5 to +7.0 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current -20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature (10 sec) 300 °C



Description

The 74LVX238 is a low voltage CMOS 3 TO 8 LINE DECODER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. If the device is enabled, 3 binary select (A, B, and C) determine which one of the outputs will go high. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go low. Tree enable inputs of the 74LVX238 are provided to ease cascade connection and application of address decoders for memory systems. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.

This 74LVX238 can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.




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