74LVX273

Features: HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC =3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL ...

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SeekIC No. : 004251618 Detail

74LVX273: Features: HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V LOW POWER DISSIPATION: ICC = 4 A (MA...

floor Price/Ceiling Price

Part Number:
74LVX273
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/29

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Product Details

Description



Features:

 HIGH SPEED: fMAX = 150 MHz (TYP.) at VCC = 3.3V
5V TOLERANT INPUTS
POWER-DOWN PROTECTION ON INPUTS
INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC =3V
LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25°C
LOW NOISE: VOLP = 0.3V (TYP.) at VCC =3.3V
SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) at VCC =3V
BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL
OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273
IMPROVED LATCH-UP IMMUNITY



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7.0 V
VI DC Input Voltage -0.5 to +7.0 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current -20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Current ± 25 mA
ICC or IGND DC VCC or Ground Current ± 50 mA
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature (10 sec) 300 °C



Description

The 74LVX273 is a low voltage CMOS OCTAL D-TYPE FLIP-FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.

Information signals applied to D inputs are transferred to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits of the 74LVX273 against static discharge, giving them 2KV ESD immunity and transient excess voltage.




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