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74LVX74

Features: Input voltage level translation from 5V to 3V Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and dynamic threshold performanceApplication·LOW input to SD (Set) sets Q to HIGH level·LOW input to CD (Clear) sets Q to LOW level·Clear and Set ar...

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SeekIC No. : 004251630 Detail

74LVX74: Features: Input voltage level translation from 5V to 3V Ideal for low power/low noise 3.3V applications Guaranteed simultaneous switching noise level and dynamic threshold performanceApplication·LOW...

74LVX74 Data Sheet

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Part Number:
74LVX74
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

 Input voltage level translation from 5V to 3V
Ideal for low power/low noise 3.3V applications
Guaranteed simultaneous switching noise level and dynamic threshold performance


Application

·LOW input to SD (Set) sets Q to HIGH level
·LOW input to CD (Clear) sets Q to LOW level
·Clear and Set are independent of clock
·Simultaneous LOW on CD and SD makes both Q and Q HIGH


Pinout

Connection Diagram


Specifications

Supply Voltage (VCC)                        -0.5V to +7.0V
DC Input Diode Current (IIK)
VI  =-0.5V                                                     -20 mA      
DC Input Voltage T/R, OE (VI)               - 0.5V to 7V
DC Diode Current (IOK)
VO  =-0.5V                                                   -20 mA
VO=  VCC + 0.5V                                          +20 mA
DC Bus I/O Voltage (VI/O)        -0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO)                                    ±25 mA
DC VCC or Ground Current
(ICC or IGND)                                              ±75 mA
Storage Temperature (TSTG)        -65qC to+150qC
Power Dissipation                                      180 mW


Description

The 74LVX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.




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