79R3051E Features
• Instruction set compatible with IDT79R3000A and
IDT79R3001 MIPS RISC CPUs
• High level of integration minimizes system cost, power
consumption
- IDT79R3000A /IDT79R3001 RISC Integer CPU
- R3051 features 4KB of Instruction Cache
- R3052 features 8KB of Instruction Cache
- All devices feature 2kB of Data Cache
- "E" Versions (Extended Architecture) feature full
function Memory Management Unit, including 64-
entry Translation Lookaside Buffer (TLB)
- 4-deep write buffer eliminates memory write stalls
- 4-deep read buffer supports burst refill from slow
memory devices
- On-chip DMA arbiter
- Bus Interface minimizes design complexity
• Single clock input with 40%-60% duty cycle
• 35 MIPS, over 64,000 Dhrystones at 40MHz
• Low-cost 84-pin PLCC packaging that's pin-/packagecompatible
with thermally enhanced 84-pin MQUAD.
• Flexible bus interface allows simple, low-cost designs
• 20, 25, 33, and 40MHz operation
• Complete software support
- Optimizing compilers
- Real-time operating systems
- Monitors/debuggers
- Floating Point Software
- Page Description Languages
79R3051E Connection Diagram
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