80C186

The Intel 80C186 is a CHMOS high integration microprocessor.In has features which are new to the 80186 family which include a DRAM refresh control unit, power-save mode and a direct numerics intertace. When used in "compatible" mode, the 80C186 is 1000} pin-for-pin compatible with the NMOS 80186 (except for 8087 applications).The "enhanced" mode of operation allows the full feature set of the SOC186 to be used.The 80C186 is upward compatible with 8086 and 8088 software and fully compatible with 80186 and 80188 software.

Features of the 80C186 are:(1)enhanced 80C86 CPU; (2)clock generator; (3)2 independent DMA channels; (4)programmable interrupt controller; (5)3 programmable 16-bit timers; (6)dynamic RAM refresh control unit; (7)programmable memory and peripheral chip select logic; (8)programmable wait state generator; (9)local bus controller; (10)power save mode; (11)system-level testing support (high impedance test mode).The following Functional Description describes the base architecture of the 80C186.The 80C186 is a very high integration i6-bit microprocessor. It combines 15-20 of the most common microprocessor system components onto one chip. The 80C186 is object code compatible with the 8086/8088 microprocessors and adds 10 new instruction types to the 8086/8088 instruction set.

The absolute maximum ratings of the 80C186 can be summarized as:(1)voltage on any pin with respect to ground:-1.0 to 7.0V;(2)storage temperature:-65 to +150;(3)ambient temperature under bias:0 to +70 ;(4)package power dissipation:1W.The state of the external interrupt input pins is also indicated. The state of the external interrupt pins is not a stored condition inside the interrupt controller,therefore the external interrupt bits cannot be written. The external interrupt request bits are set when an interrupt request is given to the interrupt controller, so if edge-triggered mode is selected, the bit in the register will be HIGH only after an inactive-to-active transition. For internal interrupt sources, the register bits are set when a request arrives and are reset when the processor acknowledges the requests.