Features: 40 MHz operationOptional clock doubler2 Mbytes of linear address space1 Kbyte of register RAM3 Kbytes of code RAM8 Kbytes of ROMRegister-to-register architectureStack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits2 peripheral interrupt handlers...
80C196EA: Features: 40 MHz operationOptional clock doubler2 Mbytes of linear address space1 Kbyte of register RAM3 Kbytes of code RAM8 Kbytes of ROMRegister-to-register architectureStack overflow/underflow mo...
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40 MHz operation
Optional clock doubler
2 Mbytes of linear address space
1 Kbyte of register RAM
3 Kbytes of code RAM
8 Kbytes of ROM
Register-to-register architecture
Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits
2 peripheral interrupt handlers (PIH) provide direct hardware handling of up to 16 peripheral interrupts
Peripheral transaction server (PTS) with high-speed, microcoded interrupt service routines
Up to 83 I/O port pins
2 full-duplex serial ports with dedicated baud-rate generators
Enhanced synchronous serial unit
8 pulse-width modulator (PWM) outputs with 8-bit resolution
16-bit watchdog timer
Sixteen 10-bit A/D channels with auto-scan mode and dedicated results registers
Serial debug unit provides read and write access to code RAM with no CPU overhead
Chip-select unit (CSU)
3 chip-select pins
Dynamic demultiplexed/multiplexed address/data bus for each chip-select
Programmable wait states (0, 1, 2, or 3) for each chip-select
Programmable bus width (8- or 16-bit) for each chip-select
Programmable address range for each chip-select
Event processor array (EPA)
4 flexible 16-bit timer/counters
17 high-speed capture/compare channels
8 output-only channels capture value of any other timer upon compare, providing easy conversion between angle and time domains
Programmable clock output signal
160-pin QFP package
Complete system development support
High-speed CHMOS technology