82510

The Intel CHMOS 82510 is designed to increase system efficiency in asynchronous environments such as modems or serial ports-including expanding performance areas: MCS-51 9-bit format and high speed async.The functional support provided in the 82510 is unparalleled-two baud rate generators/timers provide independent data rates or protocol timeouts; a crystal oscillator and smart modem I/O simplify system logic. New features---dual FIFOs and Control Character Recognition (CCR)--dramatically reduce CPU interrupts and increase software efficiency.The 82510's software versatility allows emulation of the INS8250A/16450 for IBM PC AT' compatibility or a high-performance mode, configured by 35 control registers.All interrupts are maskable at two levels.

The 82510 has the following features include:(1)multiple sampling windows; (2)two, independent, four-byte transmit and receive FIFOs with programmable threshold; (3)two, 16-bit baud rate generators/timers; (4)control character recognition; (5)CNMOS III with power down mode; (6)interrupts maskable at two levels; (7)auto echo and loopback modes; (8)seven I/O pins, dedicated and general purpose; (9)28-lead dip and plcc packages.The 82510 has a simple demultiplexed Bus Interface, which consists of a bidirectional three-state eight-bit, data bus and a three-bit address bus. An Interrupt pin along with the Read, Write and Chip Select are the remaining signals used to intertace with the CPU. The three address lines along with the Bank Pointer register are used to select the registers.The 82510 is designed to interface to all Intel microprocessor and microcontroller families.Like most other I/O based peripherals it is programmed through its registers to support a variety of functions.

The absolute maximum ratings of the 82510 are:(1)storage temperature:-65 to +150°C;(2)ambient temperature under bias:0 to +70°C;(3)voltage on any pin:-0.5 to Vcc+0.5V;(4)voltage on Vcc pin:Vss-0.5 to +7V;(5)power disspation:300mA.The 82510 has a device enable register, GER, which can be used to enable or mask-out any block interrupt request. Some of the blocks (Rx Machine, Modem, Timer) have an enable register associated with their status register which can be used to mask out the individual sources within the block. Interrupts are enabled when programmed high.