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MFG:ACTEL Package Cooled:PLCC
Part Number: A1010B
MFG: ACTEL
Package Cooled: PLCC
Description: The ACT™ 1 Series of field programmable gate arrays (FPGAs) offers a variety of package, speed, ...
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A1010B
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DataSheet
General Description
A1010B General Description
The ACT™ 1 Series of field programmable gate arrays (FPGAs) offers a variety of package, speed, and application combinations. Devices are implemented in silicon gate, 1-micron two-level metal CMOS, and they employ Actel's PLICE® antifuse technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95 to 100 percent of available logic modules.
ACT 1 devices also provide system designers with unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. Additional features include an on-chip clock driver with a hardwired distribution network. The network provides efficient clock distribution with minimum skew.
The user-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages include plastic and ceramic J-leaded chip carriers, ceramic and plastic quad flatpacks, and ceramic pin grid array.
A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered.
A1010B Maximum Ratings
VCC DC Supply Voltage2 ........0.5 to +7.0 Volts
VI Input Voltage............. 0.5 to VCC +0.5 Volts
VO Output Voltage .........0.5 to VCC +0.5 Volts
IIO I/O Sink/Source Current3 .................±20 mA
TSTG Storage Temperature .........65 to +150
VI Input Voltage............. 0.5 to VCC +0.5 Volts
VO Output Voltage .........0.5 to VCC +0.5 Volts
IIO I/O Sink/Source Current3 .................±20 mA
TSTG Storage Temperature .........65 to +150
A1010B Features
• 5V and 3.3V Families fully compatible with JEDEC
specifications
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL® Packages
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic Place and Route
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 25 MHz
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
specifications
• Up to 2000 Gate Array Gates (6000 PLD equivalent gates)
• Replaces up to 50 TTL Packages
• Replaces up to twenty 20-Pin PAL® Packages
• Design Library with over 250 Macro Functions
• Gate Array Architecture Allows Completely Automatic Place and Route
• Up to 547 Programmable Logic Modules
• Up to 273 Flip-Flops
• Data Rates to 75 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 25 MHz
• Built-In High Speed Clock Distribution Network
• I/O Drive to 10 mA (5 V), 6 mA (3.3 V)
• Nonvolatile, User Programmable
• Fabricated in 1.0 micron CMOS technology
A1010B Connection Diagram
A100P80-1TI
PDF/DataSheet Download
- Datasheet: A100P80-1TI
- File Size: 428137 KB
- Manufacturer: ETC
- Click here to Download
- ·A100P80-4TI
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