A29L800A Series

The A29L800A is an 8Mbit, 3.0 volt-only Flash memory rganized as 1,048,576 bytes of 8 bits or 524,288 words of 16
bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of ata appear on I/O0~I/O15. The A29L800A is offered in 48-ball FBGA, 44-pin SOP and 48-Pin TSOP packages. This device s designed to be programmed in-system with the standard ystem 3.0 volt VCC supply. Additional 12.0 volt VPP is not equired for in-system write or erase operations. However, the 29L800A can also be programmed in standard EPROM rogrammers.

The A29L800A has the first toggle bit, I/O6, which indicates hether an Embedded Program or Erase is in progress, or it is n the Erase Suspend. Besides the I/O6 toggle bit, the 29L800A has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The 29L800A also offers the ability to program in the Erase uspend mode. The standard A29L800A offers access times f 70 and 90ns, allowing high-speed microprocessors to perate without wait states. To eliminate bus contention the evice has separate chip enable (CE ), write enable ( WE ) nd output enable (OE ) controls.

The device requires only a single 3.0 volt power supply for oth read and write functions. Internally generated and
regulated voltages are provided for the program and erase perations.

The A29L800A is entirely software command set compatible ith the JEDEC single-power-supply Flash standard. ommands are written to the command register using tandard microprocessor write timings. Register contents serve
as input to an internal state-machine that controls the erase nd programming circuitry. Write cycles also internally latch ddresses and data needed for the programming and erase perations. Reading data out of the device is similar to reading rom other Flash or EPROM devices.

Device programming occurs by writing the proper program ommand sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the rogram pulse widths and verifies proper program  argin.

Device erasure occurs by executing the proper erase ommand sequence. This initiates the Embedded Erase lgorithm - an internal algorithm that automatically reprograms the array (if it is not already programmed) before xecuting the erase operation. During erase, the device utomatically times the erase pulse widths and verifies proper rase margin. The Unlock Bypass mode facilitates faster rogramming times by requiring only two write cycles to rogram data instead of four.

The host system can detect whether a program or erase peration is complete by observing the RY / BY pin, or by eading the I/O7 (Data Polling) and I/O6 (toggle) status bits.