A5800

The UCN5800A/L and UCN5801A/EP/LW latched-input BiMOS ICs merge high-current, high-voltage outputs with CMOS logic. The CMOS input section consists of 4 or 8 data ('D' type) latches with associated common CLEAR, STROBE, and OUTPUT ENABLE circuitry.

The power outputs are bipolar npn Darlingtons. This merged technology provides versatile, flexible interface. These BiMOS power interface ICs greatly benefit the simplification of computer or microprocessor I/O. The UCN5800A and UCN5800L each contain four latched drivers; the UCN5801A, UCN5801EP, and UCN5801LW contain eight latched drivers.

The UCN5800A/L and UCN5801A/EP/LW supersede the original BiMOS latched-input driver ICs (UCN4400A and UCN4801A). These second-generation devices are capable of much higher data input rates and will typically operate at better than 5 MHz with a 5 V logic supply. Circuit operation at 12 V affords substantial improvement over the 5 MHz figure. The CMOS inputs are compatible with standard CMOS and NMOS circuits. TTL circuits may mandate the addition of input pull-up resistors. The bipolar Darlington outputs are suitable for directly driving many peripheral/ power loads: relays, lamps, solenoids, small dc motors, etc.

All devices have open-collector outputs and integral diodes for inductive load transient suppression. The output transistors are capable of sinking 500 mA and will withstand at least 50 V in the OFF state. Because of limitations on package power dissipation, the simultaneous operation of all drivers at maximum rated current can only be accomplished by a reduction in duty cycle. Outputs may be paralleled for higher load current capability.

The UCN5800A is furnished in a standard 14-pin DIP; the UCN5800L and UCN5801LW in surface-mountable SOICs; the UCN5801A in a 22-pin DIP with 0.400" (10.16 mm) row centers; the UCN5801EP in a 28-lead PLCC.