A65H83181

The A65H73361 and A65H83181 are 128k words by 36 bits and 256k words by 18 bits late write synchronous 4Mb SRAMS built using high performance CMOS process.

The differential clock are used to control the timing of read/write operation and all internal operations are selftimed. The positive edge triggered CK clock input controls all addresses write-enables and Synchronous select and data ins are registered.

The data outs are controlled by the output registers off the next positive clock edge to be updated. The internal write buffer enables write data to be accepted on the rising edge of the clock one cycle after address and control signals.

The SRAM uses HSTL I/O interfaces with programmable impedance output drivers allowing the outputs to match the impedance of the circuit traces which reduces signal reflections.