Features: 12-bit, 65 MSPS dual ADC Differential input with 100 input impedance Full-scale analog input: 296 mV p-p 170 MHz, 3 dB bandwidth SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN) SFDR (−9 dBFS): 77 dBFS (70 MHz AIN), 73 dBFS (140 MHz AIN) 435 mW per channel Dual pa...
AD15252: Features: 12-bit, 65 MSPS dual ADC Differential input with 100 input impedance Full-scale analog input: 296 mV p-p 170 MHz, 3 dB bandwidth SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 M...
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Parameter | Rating |
AVDD to AGND DRVDD to DRGND DRGND to AGND DRVDD to AVDD Analog Inputs Digital Outputs CLK Operational Case Temperature Storage Temperature Range Lead Temperature: Infrared, 15 sec |
−0.3 V, +3.9 V −0.3 V, +3.9 V −0.3 V, +0.3 V −3.9 V, +3.9 V −0.3 V, AVDD + 0.3 V −0.3 V, DRVDD + 0.3 V −0.3 V, AVDD + 0.3 V −40°C to 85°C −65°C to 150°C 230°C |
The AD15252 is a dual, 12-bit, 65 MSPS, analog-to-digital converter (ADC). It features a differential front-end amplification circuit followed by a sample-and-hold amplifier and multistage pipeline ADC. It is designed to operate with a 3.3 V analog supply and a 2.5 V/3.3 V digital supply. Each input is fully differential, ac-coupled, and terminated in 100 input impedances. The full-scale differential signal input range is 296 mV p-p.
Two parallel, 12-bit digital output buses provide data flow from the ADCs. The digital output data is presented in either straight binary or twos complement format. Out-of-range (OTR) signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow. Dual single-ended clock inputs control all internal conversion cycles. A duty cycle stabilizer allows wide variations in the clock duty cycle while maintaining excellent performance. The AD15252 is optimized for applications in antijam global positioning receivers and is well suited for communications applications.