AD1958

The AD1958 has two DAC channels arranged as a stereo pair with single-ended analog outputs. Each channel has its own independently programmable attenuator, adjustable in 16384 linear steps. Digital inputs are supplied through a serial data input pin, SDATA, a frame clock, LRCLK, and a bit clock, BLCK.

Each analog output pin sits at a dc level of VREF (present at FILTR), and swings ± 1.585 V for a 0 dB digital input signal. A single op amp third-order external low-pass filter is recommended to remove high-frequency noise present on the output pins. The output phase can be changed in an SPI control register to accommodate inverting and noninverting filters. Note that the use of op amps with low slew rate or low bandwidth may cause high frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components.

The FILTB and FILTR pins should be bypassed by external capacitors to ground. The FILTB pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. The voltage at the VREF pin, FILTR (VREF ~ 2.39 V) can be used to bias external op amps used to filter the output signals.

The DAC master clock frequency is 256 fS for the 32 kHz48 kHz range (8* interpolation, see Table I). For the 96 kHz range (4*interpolation) this is 128 fS. At 192 kHz (2* interpolation), this is 64 fS. It is supplied internally from the PLL clock system when MCLK mode is set to Output in the PLL Control Register.

When the MCLK mode is changed to Input, it must be supplied from an external source connected to MCLK. The output from the 27 MHz PLL clock is disabled in this case.