AD1959 General Description
AD1959 Maximum Ratings
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V
AVDD to DGND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V
Digital Inputs . . . . . . . . .. . DGND 0.3 V to DVDD + 0.3 V
Analog Inputs . . . . . . . . .. . AGND 0.3 V to AVDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to + 0.3 V
Reference Voltage . . . . . . . . . . . . . . .. . . . . (AVDD + 0.3)/2
Soldering (10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
AD1959 Features
5 V Stereo Audio DAC System
Accepts 16-Bit/20-Bit/24-Bit Data
Supports 24 Bits, 192 kHz Sample Rate
Accepts a Wide Range of Sample Rates Including:
32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz
Multibit Sigma-Delta Modulator with Data Directed
Scrambling
Single-Ended Output for Easy Application
94 dB THD + N
108 dB SNR and Dynamic Range
75 dB Stopband Attenuation
Clickless Volume Control
Hardware and Software Controllable Clickless Mute
Serial (SPI) Control for: Serial Mode, Number of Bits,
Sample Rate, Volume, Mute, De-Emphasis and Output Phase
Digital De-Emphasis Processing for 32 kHz, 44.1 kHz,and 48 kHz Sample Rates
Programmable Dual Fractional-N PLL Clock Generator
27 MHz Master Clock Input/Oscillator
Generated System Clocks
SCLK0: 33.8688 MHz
SCLK1: 384/256 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/96 kHz)
SCLK2: 512 fS (32 kHz/44.1 kHz/48 kHz/88.2 kHz/96 kHz)/22.5792 MHz
Better than 100 ps RMS Clock Jitter
Flexible Serial Data Port with Right-Justified, Left-Justified, I2S-Compatible, and DSP Serial Port Modes
28-Lead SSOP Plastic Package
AD1959 Typical Application
AD1959 Connection Diagram
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