Features: AD5330: Single 8-Bit DAC in 20-Lead TSSOP
AD5331: Single 10-Bit DAC in 20-Lead TSSOP
AD5340: Single 12-Bit DAC in 24-Lead TSSOP
AD5341: Single 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 115
A @ 3 V, 140 A @ 5 VPower-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin2.5 V to 5.5 V Power SupplyDouble-Buffered Input LogicGuaranteed Monotonic by Design Over All CodesBuffered/Unbuffered Reference Input OptionsOutput Range: 0VREF or 02 VREFPower-On Reset to Zero Voltsimultaneous Update of DAC Outputs via LDAC PinAsynchronous CLR FacilityLow Power Parallel Data InterfaceOn-Chip Rail-to-Rail Output Buffer AmplifiersTemperature Range: 40 to +105Pinout
Specifications
| Resolution (Bits) |
10bit |
| DAC Update Rate |
143kSPS |
| DAC Settling Time |
7s |
| # DAC Outputs |
1 |
| DAC Type |
Voltage Out |
| DAC Input Format |
Par |
| Output FSR |
(Uni 2Vref),(Uni Vref) |
| Ref Int/Ext |
Ext |
| Supply Vnom |
Single(+2.7),Single(+3),Single(+3.3),Single(+5) |
| Pwr Diss |
1.25mW |
| Package |
SOP |
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Digital Input Voltage to GND . . . . . .. . 0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . . 0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . .0.3 V to VDD + 0.3 V
VOUT to GND . . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . .. 40 to +105
Storage Temperature Range . . . . . . . . . . 65 to +150
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (TJ max TA)/JA mW
JA Thermal Impedance (20-Lead TSSOP) . . . . . 143/W
JA Thermal Impedance (24-Lead TSSOP) . . . . . 128/W
JA Thermal Impedance (20-Lead TSSOP) . . . . . . 45/W
JC Thermal Impedance (24-Lead TSSOP) . . . . . . 42/WDescriptionThe AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and12-bit DACS. They operate from a 2.5 V to 5.5 V supply consumingjust 115 A at 3 V, and feature a power-down mode thatfurther reduces the current to 80 nA. These devices incorporatean on-chip output buffer that can drive the output to bothsupply rails, while the AD5330, AD5340, and AD5341 allow achoice of buffered orunbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel interface.CS selects the device and data is loaded into the input registerson the rising edge of WR.
The GAIN pin allows the output range to be set at 0 V to LDACInput data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.or 0 V to 2 * VREF..
An asynchronous CLR input is also provided, which resets thecontents of the Input Register and the DAC Register to all zeros.These devices also incorporate a power-on reset circuit that ensuresthat the DAC output powers on to 0 V and remains thereuntilvalid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in ThinShrink Small Outline Packages (TSSOP).
AD5331 Data Sheet
