AD5341

V_DD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . 0.3 V to V_DD + 0.3 V
Digital Output Voltage to GND . . . . . 0.3 V to V_DD + 0.3 V
Reference Input Voltage to GND . . . . 0.3 V to V_DD + 0.3 V
V_OUT to GND . . . . . . . . . . . . . . . . . . . 0.3 V to V_DD + 0.3 V
Operating Temperature Range
   Industrial (B Version) . . . . . . . . . . . . . . . 40°C to +105°C
Storage Temperature Range . . . . . . . . . . .65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package
   Power Dissipation . . . . . . . . . . . . . . . (T_J max TA)/_JA mW
     _JA Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W
     _JA Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W
     _JA Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W
     _JC Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W
Reflow Soldering
     Peak Temperature . . . . . . . . . . . . . . . . . . . .220 +5/0°C
     Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 A at 3 V, and feature a power-down mode that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, while the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input.

The AD5330/AD5331/AD5340/AD5341 have a parallel interface.CS selects the device and data is loaded into the input registers on the rising edge of WR.

The GAIN pin allows the output range to be set at 0 V to V_REF or 0 V to 2 * V_REF.

Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.

An asynchronous CLR input is also provided, which resets the contents of the Input Register and the DAC Register to all zeros.These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.

The AD5330/AD5331/AD5340/AD5341 are available in Thin Shrink Small Outline Packages (TSSOP).