Series: -
Number of Converters: 1
Number of Bits: 16
Sampling Rate (Per Second): 100k
Packaging: Tube
Mounting Type: Through Hole
Operating Temperature: 0°C ~ 70°C
Number of Inputs and Type: 1 Single-Ended, Bipolar
Package / Case: 16-DIP (0.300", 7.62mm)
Supplier Device Package: 16-PDIP
Voltage Supply Source: Analog and Digital, Dual ±
Data Interface: DSP, Serial
Power Dissipation (Max): 480mW
Manufacturer: Analog Devices Inc
Pinout
DescriptionThe AD677 is a multipurpose 16-bit serial output analog-to-digital converter and uses a switched-capacitor/charge redistribution architecture to achieve a 100 kSPS conversion rate (10 ms total conversion time).The advantage of Overall performance is digitally correcting internal nonlinearities through on-chip autocalibration.The AD677 circuitry is divided into two monolithic chips-a digital control chip fabricated on Analog Devices DSP CMOS process and an analog ADC chip fabricated on our BiMOS II process. Both chips are contained in a single package.The AD677 has the following features:(1)autocalibrating;(2)on-chip sample-hold function;(3)Serial Output;(4)16 bits no missing codes;(5)±1 LSB INL;(6)99 dB THD;(7)92 dB s/(n+d);(8)1 MHz full power bandwidth.
AD677JN also has some digital specifications((for all grades Tmin to Tmax, Vcc =+12 V±5%, Vee =12 V ± 5%, Vdd=+5 V±10%):One is logic inputes:(1)high level input voltage is 2.0 V min and VDD + 0.3 V max.(2)low level input voltage is -0.3 V max and 0.8 V min; (3)high level input current is -10 uA min and +10 V max when VIH is VDD ;(4)low level input current is -10 uA min and +10 uA when VIH is 0V.(5)input capacitance is 10 pF typ.The other is logic outputs:(1)high level output voltage is VDD 1 V V min when IOH is 0.1 mA;(2)low level output voltage is 0.4V max when IOL is 1.6 mA.
Some timing specifications of AD677JN have been concluded into several points as below(TMIN to TMAX, VCC =+12 V ± 5%, VEE =12 V ± 5%, VDD= +5 V ± 10%):(1)calibration time is 85532 tCLK max;(2)sampling time is 2 Us min;(3)sample low is 100 ns min;(4)sample to busy delay is 30 ns typ and 75 ns max;(5)first clk delay is 50 ns min;(6)clk to busy delay is 180 ns typ and 300 ns max.(7)clk to sdata valid is 50 ns min, 100 ns typ and 300 ns max.etc.
Parameters: | Technical/Catalog Information | AD677JN |
| Vendor | Analog Devices Inc |
| Category | Integrated Circuits (ICs) |
| Number of Bits | 16 |
| Package / Case | 16-DIP (300 mil) |
| Data Interface | Serial |
| Packaging | Tube |
| Sampling Rate (Per Second) | 100k |
| Operating Temperature | 0°C ~ 70°C |
| Voltage Supply Source | Analog and Digital, Dual ± |
| Number of Inputs and Type | 1 Single-Ended, Bipolar |
| Number of Converters | 1 |
| Power Dissipation (Max) | 480mW |
| Drawing Number | * |
| Lead Free Status | Contains Lead |
| RoHS Status | RoHS Non-Compliant |
| Other Names | AD677JN
AD677JN
|
AD677JN Data Sheet
