AD7555

The AD7555 has the following features including Resolution: ±4 7 /2 Digits BCD or ±20k Count Binary Capabiiity for 5 712 Digit Resolution or Custom Data Formats;Data Format: Multiplexed SCD (for Dispiayf and Serial Count(for I=xternal Linearizativn, Data Reformatting, or Microprocessor Interface);Accuracy: ±1 Count in ±20k Counts;Scale Factor Drift: 0.2ppm/°C Using Only Medium-prevision Op Amps.

The AD7555 is a 4 112 digit,monolithic CMOS,quad slope integrating ADC subsystem designed for display or microprocessor interface applications. Use of the high resolation enable input expands the display format to 5 I/2 With 5C0 (serial Count OutJ connected to SCi (Serial Count In), the output data format is multiplexed BCD suitable for visual display purposes. As an added feature, 5Cd can also be used with rate multipliers for linearixation, or with BCD or binary counters for data reformatting (up to 2DDk binary counts).The quad slope conversion algorithm (Analog Deices patent No. 3872466) converts the external amplifier's input drift errors to a digital number and subsequently reduces the total system drift error to a second order effort. Using only inexpensive, medium-precision amplifiers a scale factor drift of 0.2ppm/°C is achieved.

Component limitations such as switch leakage, as well as operational amplifier offser voltage and bias current (and the temperature dependency of these errors), are major obstacles when designing high resolution integrating A/D converters.The AD7555 however, utilizers a patented quad slope convertion technique (Analog Devices Patent NO.3872466) to reduce the effects of such errors to second order effects.Other advantages of the quad slope ieehnique include bipolar operation using a single positive voltage reference, and the fact that since the c.omparator prnpagarinn delay is constant hysteresis effects are eliminated. (This is because the comparator always approaches the zero crossing #rom the same direction).A reset phase (phase 0) is initiated can the 4th DMC after conversion is complete.SCC returns low at the phase Q comparauar crossing indicating a conversion start.If the DMC oscillator is set up to free run (C8 in Figure 6b causes DMC to run at about 1.5kHz), the AL77555 will consinuously concert and update the displays.