AD9238BST-40

The AD9238BST-40 is one member of the AD9238 series.The AD9238 is a dual, 3 V, 12-bit, 20 MSPS/40 MSPS/65 MSPS analog-to-digital converter. It features dual high performance sample-and-hold amplifi ers and an integrated voltage reference. The AD9238 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy and guarantee no missing codes over the full operating temperature range at data rates up to 65 MSPS.

Features of the AD9238BST-40 are:(1)integrated dual 12-bit analog-to-digital converters; (2)single 3 V supply operation (2.7 V to 3.6 V); (3)SNR = 70 dBc (to nyquist, AD9238-65); (4)SFDR = 85 dBc (to nyquist, AD9238-65); (5)low power: 600 mW at 65 MSPS; (6)differential input with 500 MHz 3 dB bandwidth; (7)on-chip reference and SHA; (8)flexible analog input: 1 V p-p to 2 V p-p range; (9)offset binary or twos complement data format; (10)clock duty cycle stabilizer.The wide bandwidth, differential SHA allows for a variety of user selectable input ranges and offsets including single-ended applications. It is suitable for various applications including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate. The AD9238 is suitable for applications in communications, imaging, and medical ultrasound.

The absolute maximum ratings of the AD9238BST-40 can be summarized as:(1)operating temperature:-45 to 85;(2)storage temperature:-65 to 150;(3)junction temperature:150;(4)lead temperature(10s):300;(5)AVDD:-0.3 to 3.9V;(6)DRVDD:-0.3 to 3.9V.Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability.The AD9238 provides separate clock inputs for each channel. The optimum performance is achieved with the clocks operated at the same frequency and phase. Clocking the channels asynchronously may degrade performance signii cantly. In some applications, it is desirable to skew the clock timing of adjacent channels. The AD9238's separate clock inputs allow for clock timing skew (typically ±1 ns) between the channels without signii cant performance degradation.