AD9281

Features:

Complete Dual Matching ADC
Low Power Dissipation: 225 mW (+3 V Supply)
Single Supply: 2.7 V to 5.5 V
Differential Nonlinearity Error: 0.1 LSB
On-Chip Analog Input Buffers
On-Chip Reference
Signal-to-Noise Ratio: 49.2 dB
Over Seven Effective Bits
Spurious-Free Dynamic Range: 65 dB
No Missing Codes Guaranteed
28-Lead SSOP




Pinout

Specifications

AVDD AVSS 0.3 +6.5 V
DVDD DVSS0.3 +6.5 V
AVSS DVSS 0.3 +0.3 V
AVDD DVDD 6.5 +6.5 V
Digital Outputs DVSS0.3 DVDD + 0.3 V
AINA, AINB AVSS1.0 AVDD + 0.3 V
VREF AVSS 0.3 AVDD + 0.3 V
REFSENSE AVSS0.3 AVDD + 0.3 V
REFT, REFB AVSS0.3 AVDD + 0.3 V






Description

The AD9281 is a complete dual channel, 28 MSPS, 8-bit CMOS ADC. The AD9281 is optimized specifically for applications where close matching between two ADCs is required (e.g., I/Q channels in communications applications). The 28 MHz sampling rate and wide input bandwidth will cover both narrow- band and spread-spectrum channels. The AD9281 integrates two 8-bit, 28 MSPS ADCs, two input buffer amplifiers, an internal voltage reference and multiplexed digital output buffers.

Each ADC incorporates a simultaneous sampling sample-and-hold amplifier at its input. The analog inputs are buffered; no external input buffer op amp will be required in most applications. The ADCs are implemented using a multistage pipeline architecture that offers accurate performance and guarantees no missing codes. The outputs of the ADCs are ported to a multiplexed digital output buffer. The AD9281 is manufactured on an advanced low cost CMOS
process, operates from a single supply from 2.7 V to 5.5 V, and consumes 225 mW of power (on 3 V supply). The AD9281 input structure accepts either single-ended or differential signals, providing excellent dynamic performance up to and beyond 14 MHz Nyquist input frequencies.