AD9288BSTZ-100

The AD9288BSTZ-100 is one member of the AD9288 series.The AD9288 is a dual 8-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits and is optimized for low cost, low power, small size and ease of use.The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range.Each channel can be operated independently.The AD9288 evaluation board offers an easy way to test the AD9288. It provides a means to drive the analog inputs singleendedly or differentially. The two encode clocks are easily accessible at on-board SMB connectors J2, J7. These clocks are buffered on the board to provide the clocks for an on-board DAC and latches.

Features of the AD9288BSTZ-100 are:(1)dual 8-Bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC; (2)low power: 90 mW at 100 MSPS per channel; (3)on-chip reference and track/holds; (4)475 MHz analog bandwidth each channel; (5)SNR = 47 dB @ 41 MHz; (6)1 V p-p analog input range each channel; (7)single +3.0 V supply operation (2.7 V3.6 V); (8)standby mode for single channel operation; (9)twos complement or offset binary output mode; (10)output data alignment mode.

The absolute maximum ratings of the AD9288BSTZ-100 can be summarized as:(1)VD, VDD:4V;(2)analog inputs:0.5 V to VD + 0.5 V;(3)digital inputs:0.5 V to VDD+0.5 V;(4)digital output current:20 mA;(5)storage temperature:-65 to +150;(6)operating temperatur:-55 to +125;(7)maximum junction temperature:175;(8)maximum case temperature:150.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.The AD9288 ADC architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine the 5 MSBs and drive a 3-bit flash. Each stage provides sufficient overlap and error correction allowing optimization of comparator accuracy. The input buffers are differential and both sets of inputs are internally biased.