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MFG:ADI D/C:09
Part Number: AD9411
MFG: ADI
D/C: 09
Description: The AD9411 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance,...
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AD9411
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DataSheet
General Description
AD9411 General Description
The AD9411 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 200 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution.
The ADC requires a 3.3 V power supply and a differential sample clock for full performance operation. The digital outputs are LVDS compatible and support both twos complement and offset binary format. A data clock output is available to ease data capture.
Fabricated on an advanced BiCMOS process, the AD9411 is available in a 100-lead surface-mount plastic package (e-PAD TQFP-100) specified over the industrial temperature range (40°C to +85°C).
AD9411 Maximum Ratings
| Parameter | Rating |
| AVDD, DRVDD Analog Inputs Digital Inputs REFIN Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature JA1 |
4 V 0.5 V to AVDD +0.5 V 0.5 V to DRVDD +0.5 V 0.5 V to AVDD +0.5 V 20 mA 55ºC to +125°C 65ºC to +150°C 150°C 150°C 25°C/W, 32°C/W |
AD9411 Features
SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS
ENOB of 9.8 @ fIN up to 70 MHz @ 200 MSPS (0.5 dBFS)
SFDR = 80 dBc @ fIN up to 70 MHz @ 200 MSPS (0.5 dBFS)
Excellent linearity:
DNL = ±0.15 LSB (typical)
INL = ±0.25 LSB (typical)
LVDS output levels
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.25 W typical @ 200 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Clock duty cycle stabilizer
Pin compatible to LVDS mode AD9430
ENOB of 9.8 @ fIN up to 70 MHz @ 200 MSPS (0.5 dBFS)
SFDR = 80 dBc @ fIN up to 70 MHz @ 200 MSPS (0.5 dBFS)
Excellent linearity:
DNL = ±0.15 LSB (typical)
INL = ±0.25 LSB (typical)
LVDS output levels
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.25 W typical @ 200 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Clock duty cycle stabilizer
Pin compatible to LVDS mode AD9430
AD9411 Typical Application
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
AD9411 Connection Diagram
AD9411
PDF/DataSheet Download
- Datasheet: AD9411
- File Size: 1874201 KB
- Manufacturer: AD
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