Features: Low phase noise, phase-locked loopOn-chip VCO tunes from 2.55 GHz to 2.95 GHzExternal VCO/VCXO to 2.4 GHz optionalOne differential or two single-ended reference inputsReference monitoring capabilityAuto and manual reference switchover/holdover modesAutorecover from holdoverAccepts refere...
AD9516-0: Features: Low phase noise, phase-locked loopOn-chip VCO tunes from 2.55 GHz to 2.95 GHzExternal VCO/VCXO to 2.4 GHz optionalOne differential or two single-ended reference inputsReference monitoring ...
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Primary Clock Function | Clean Up,Distribution,Generation |
+Supply Voltage (V) | 3.3V |
Max Input Frequency | 2.4GHz |
# of Outputs | 14 |
Max f-out (MHz) | 2950MHz |
I/O Interface | Serial |
Package | 64-LFCSP |
Output Logic | CMOS,LVDS,LVPECL |
Product Description | Multi-Output Clock Generator |
Parameter or Pin | With Respect to | Rating |
VS, VS_LVPECL VCP REFIN,REFIN REFIN RSET CPRSET CLK, CLKCLK SCLK, SDIO, SDO, CSOUT0,OUT0, OUT1,OUT1, OUT2,OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6 OUT7, OUT7, OUT8, OUT8, OUT9, OUT9SYNC REFMON, STATUS, LD Junction Temperature1 Storage Temperature Range Lead Temperature (10 sec) |
GND GND GND REFIN GND GND GND CLK GND GND GND GND GND |
−0.3 V to +3.6 V −0.3 V to+5.8 V −0.3 V to VS + 0.3 V −3.3 V to +3.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −1.2 V to +1.2 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V 150°C −65°C to +150°C 300°C |
The AD9516-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz may be used.
The AD9516-0 emphasizes low jitter and phase noise to maximize data converter performance, and can benefit other applications with demanding phase noise and jitter requirements.
The AD9516-0 features six LVPECL outputs (in three pairs); four LVDS outputs (in two pairs); and eight CMOS outputs (two per LVDS output). The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.
The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. A separate LVPECL power supply can be from 2.375 V to 3.6 V.
The AD9516-0 is specified for operation over the industrial range of −40°C to +85°C.
1 AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-0 is used it is referring to that specific member of the AD9516 family.