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MFG:ADI D/C:09
Part Number: AD9540
MFG: ADI
D/C: 09
Description: The AD9540 is Analog Devices' first dedicated clocking product specifically designed to support the ex...
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AD9540
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DataSheet
General Description
AD9540 General Description
The AD9540 is Analog Devices' first dedicated clocking product specifically designed to support the extremely stringent clock-ing requirements of the highest performance data converters. The device features high performance PLL circuitry, including a flexible 200 MHz phase frequency detector and a digitally controlled charge pump current. The device also provides a low jitter, 655 MHz CML-mode, PECL-compliant output driver with programmable slew rates. External VCO rates up to 2.7 GHz are supported. Extremely fine tuning resolution (steps less than 2.33 µHz) is another feature supported by this device. Informa-tion is loaded into the AD9540 via a serial I/O port that has a device write-speed of 25 Mb/s. The AD9540 frequency divider block can also be programmed to support a spread spectrum mode of operation.
The AD9540 is specified to operate over the extended automotive range of −40°C to +85°C.
AD9540 Maximum Ratings
| Parameter | Rating |
| Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Digital I/O Supply Voltage (DVDD_I/0) Charge Pump Supply Voltage (CPVDD) Maximum Digital Input Voltage Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Thermal Resistance (JA) |
2 V 2 V 3.6 V 3.6 V −0.5 V to DVDD_I/O + 0.5 V −65°C to +150°C −40°C to +125°C 300°C 150°C 26°C/W |
AD9540 Features
Excellent intrinsic jitter performance
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase fre-quency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 programmable internal clock rates
Programmable edge delay with 93 fS resolution
1.8 V supply for device operation
3.3 V supply for I/O, CML driver, and charge pump output
Software controlled power-down
48-lead LFCSP package
Programmable charge pump current (up to 4 mA)
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase fre-quency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 programmable internal clock rates
Programmable edge delay with 93 fS resolution
1.8 V supply for device operation
3.3 V supply for I/O, CML driver, and charge pump output
Software controlled power-down
48-lead LFCSP package
Programmable charge pump current (up to 4 mA)
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
AD9540 Typical Application
Clocking high performance data converters
Base station clocking applications
Network (SONET/SDH) clocking
Gigabit Ethernet (GbE) clocking
Instrumentation clocking circuits
Base station clocking applications
Network (SONET/SDH) clocking
Gigabit Ethernet (GbE) clocking
Instrumentation clocking circuits
AD9540 Connection Diagram
AD9540
PDF/DataSheet Download
- Datasheet: AD9540
- File Size: 1927594 KB
- Manufacturer: AD
- Click here to Download
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- ·AD9000SD
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- ·AD9002
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- ·AD9002AD
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- ·AD9002AJ
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- ·AD9002BD
- AD [Analog Devices]
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AD9540 Relative Products
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