AD9864

The AD9864 is a general-purpose narrow-band IF subsystem that digitizes a low level 10 MHz to 300 MHz IF input with a signal bandwidth ranging from 6.8 kHz to 270 kHz. The signal chain of the AD9864 consists of an LNA, a mixer, a band-pass - ADC, and a decimation filter with programmable decimation factor.

The input LNA is a fixed gain block with an input impedance of approximately 370 ?||1.4 pF. The LNA input is single-ended and self-biasing, allowing the input IF to be ac-coupled. The LNA can be disabled through the serial interface, providing a fixed 16 dB attenuation to the input signal.  The LNA drives the input port of a Gilbert-type active mixer. The mixer LO port is driven by the on-chip LO buffer, which can be driven externally, single-ended or differential. The LO buffer inputs are self-biasing and allow the LO input to be  ac-coupled. The open-collector outputs of the mixer drive an external resonant tank consisting of a differential LC network tuned to the IF of the band-pass - ADC. 

The external differential LC tank forms the resonator for the first stage of the band-pass - ADC. The tank LC values must be selected for a center frequency of fCLK/8, where fCLK is the sample rate of the ADC. The fCLK/8 frequency is the IF digitized by the band-pass - ADC. On-chip calibration allows stan-dard tolerance inductor and capacitor values. The calibration is typically performed once at power-up.The ADC contains a sixth order multibit band-pass -? modu-ator that achieves very high instantaneous dynamic range over a narrow frequency band centered at fCLK/8. The modulator  output is quadrature mixed to baseband and filtered by three cascaded linear phase FIR filters to remove out-of-band noise.  The first FIR filter is a fixed decimate by 12 using a fourth order comb filter. The second FIR filter also uses a fourth order comb filter with programmable decimation from 1 to 16. The third FIR stage is programmable for decimation of either 4 or 5. The cascaded decimation factor is programmable from 48 to 960. The decimation filter data is output via the synchronous serial interface (SSI) of the chip. 

Additional functionality built into the AD9864 includes LO and clock synthesizers, programmable AGC, and a flexible synchro-nous serial interface for output data. The LO synthesizer is a programmable PLL consisting of a low noise phase frequency detector (PFD), a variable output current charge pump (CP), a 14-bit reference divider, A and B counters, and a dual modulus prescaler. The user only needs to add an appropriate loop filter and VCO for complete operation.  The clock synthesizer is equivalent to the LO synthesizer with the following differences: 
It does not include the prescaler or A counter.
It includes a negative resistance core used for VCO  generation.

The AD9864 contains both a variable gain amplifier (VGA) and a digital VGA (DVGA). Both of these can operate manually or automatically. In manual mode, the gain for each is programmed through the SPI. In automatic gain control mode, the gains are adjusted automatically to ensure the ADC does not clip and that the rms output level of the ADC is equal to a programmable ref-erence level.

The VGA has 12 dB of attenuation range and is implemented by adjusting the ADC full-scale reference level. The DVGA gain is implemented by scaling the output of the decimation filter. The DVGA is most useful in extending the dynamic range in nar-row-band applications requiring 16-bit I and Q data format. 

The SSI provides a programmable frame structure, allowing  24-bit or 16-bit I and Q data and flexibility by including  attenuation and RSSI data if required.