Features: 40 MHz correlated double sampler (CDS) 0 dB to 18 dB, 9-bit variable gain amplifier (VGA) 40 MSPS analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing driver Precision Timing Core with <550 ps resolution On-chip 3 V horizontal and RG...
AD9942: Features: 40 MHz correlated double sampler (CDS) 0 dB to 18 dB, 9-bit variable gain amplifier (VGA) 40 MSPS analog-to-digital converter (ADC) Black level clamp with variable level control Complete ...
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Parameter | Rating |
AVDD_X and TCVDD_X to AVSS_X HVDD_X and RGVDD_X to HVSS_X and RGVSS_X DVDD_X and DRVDD_X to DVSS_X and DRVSS_X Any VSS_X to Any VSS_X Digital Outputs to DRVSS_X SCK_X, SL_X, and SDATA_X to DVSS_X RG_X to RGVSS_X H1X to H4X to HVSS_X REFT_X, REFB_X, and CCDIN_X to AVSS_X Junction Temperature Lead Temperature (10 sec) |
3−0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to RGVDD + 0.3 V −0.3 V to HVDD + 0.3 V −0.3 V to AVDD + 0.3 V 150°C 300°C |
The AD9942 is a highly integrated dual-channel CCD signal processor for digital still camera applications. Each channel is specified at pixel rates of up to 40 MHz. The AD9942 consists of a complete analog front end with analog-to-digital conversion, combined with a programmable timing driver. The Precision Timing Core allows high speed clocks to be adjusted with 550 ps resolution.
The analog front end uses black level clamping and includes a VGA, a 40 MSPS ADC, and a CDS. The timing driver provides the high speed CCD clock drivers for RG_A, RG_B, and the H1A to H4A and H1B to H4B outputs. The 6-wire serial interface is used to program the AD9942.
Available in a space-saving, 9 mm × 9 mm, CSP_BGA package, the AD9942 is specified over an operating temperature range of −25°C to +85°C.