AD9959

The AD9959 consists of four DDS cores that provide indepen-dent frequency, phase, and amplitude control on each channel. This flexibility can be used to correct imbalances between signals due to analog processing such as filtering, amplification, or PCB layout-related mismatches. Since all channels share a common system clock, they are inherently synchronized. Synchronization of multiple devices is supported.

The AD9959 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9959 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.

The AD9959 serial I/O port offers multiple configurations to provide significant flexibility. The serial I/O port offers an SPI-compatible mode of operation that is virtually identical to the SPI operation found in earlier Analog Devices' DDS products. Flexibility is provided by four data pins (SDIO_0:3) that allow four programmable modes of serial I/O operation.

The AD9959 uses advanced DDS technology that provides low power dissipation with high performance. The device incorporates four integrated high speed 10-bit DACs with excellent wideband and narrowband SFDR. Each channel has a dedicated 32-bit frequency tuning word, 14-bits of phase offset, and a 10-bit output scale multiplier.

The DAC outputs are supply referenced and must be terminated into AVDD by a resistor or an AVDD center-tapped transfor-mer. Each DAC has its own programmable reference to enable different full-scale currents for each channel.

The DDS acts as a high resolution frequency divider with the REF_CLK as the input and the DAC providing the output. The REF_CLK input source is common to all channels and can be driven directly or used in combination with an integrated REF_CLK multiplier (PLL) up to a maximum of 500 MSPS. The PLL multiplication factor is programmable from 4 to 20, in integer steps. The REF_CLK input also features an oscillator circuit to support an external crystal as the REF_CLK source. The crystal must be between 20 MHz and 30 MHz. The crystal can be used in combination with the REF_CLK multiplier.

The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) is powered by a 1.8 V supply. The digital I/O interface (SPI) operates at 3.3 V and requires the pin labeled DVDD_I/O (Pin 49) be connected to 3.3 V.

The AD9959 operates over the industrial temperature range of −40°C to +85°C.