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ADM1073

Features: ` Precision inrush linear current limit` Soft start inrush current limit profiling` Precision maximum on-time in current limit` Maximum on-time modulated by FET drain voltage for additional SOA protection` Adjustable PWM retry scheme and multiple device cascading capability for charging ...

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SeekIC No. : 004275574 Detail

ADM1073: Features: ` Precision inrush linear current limit` Soft start inrush current limit profiling` Precision maximum on-time in current limit` Maximum on-time modulated by FET drain voltage for additiona...

ADM1073 Data Sheet

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Part Number:
ADM1073
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/29

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Product Details

Description



Features:

` Precision inrush linear current limit
` Soft start inrush current limit profiling
` Precision maximum on-time in current limit
` Maximum on-time modulated by FET drain voltage for additional SOA protection
` Adjustable PWM retry scheme and multiple device cascading capability for charging large capacitive loads
` Limited number of PWM cycles for FET SOA protection under short circuit condition
` Ability to configure device as continuous autoretry with a 5-second cooling period
` Shunt regulator topology to allow very large transient input supplies
` Separate UV and OV pins for programming allowable input supply window
` Programmable OV hysteresis using current source into pin when supply is high
` Programmable UV hysteresis using current sink from pin when supply is low
` PWRGD output indicates when capacitor charging complete
` SPLYGD output indicates when supply is within valid window
` LATCHED output indicates the end of the retry cycle before load capacitance is charged
`SHDN input for user-commanded shutdown
` RESTART input for user-triggered 5-second shutdown and autorestart- virtual card reseat




Application

· Central office switching
· Telecommunication and data communication equipment
−48 V distributed power systems
· Negative power supply control
· High availability servers
−48 V power supply modules
· Disk arrays




Pinout

Connection Diagram

ADM1073 Diagram




Specifications

Parameter Rating
Supply Voltage (VDD − VEE) .. −0.3 V to −200.0 V
Maximum Shunt Supply Voltage, ...... VSS 16 V
SENSE Pin ..................−2 V to +2 V
GATE Pin ................ −0.3 V to +16 V
UV Pin ...................−0.3 V to +6 V
OV Pin ...................−0.3 V to +6 V
SS Pin ...................−0.3 V to +6 V
TIMER Pin ................ −0.3 V to +6 V
DRAIN Pin ................ −0.3 V to +6 V
SHDN Pin ................ −0.3 V to +16 V
SPLYGD Pin ...............−0.3 V to +16 V
LATCHED Pin ..............−0.3 V to +16 V
PWRGD Pin ...............−0.3 V to +16 V
RESTART Pin .............. −0.3 V to +16 V
Maximum Junction Temperature ........125°C
Operating Temperature Range.. −40°C to +85°C
Continuous Power Dissipation......180 mW
Storage Temperature Range.. −65°C to +150°C
Lead Temperature (Soldering, 10 s).....300°C

Operating Range(V) -18 to -80
Other Inputs RESTARTb,SHDNb
Other Outputs LATCHEDb,PWRGDb,SPLYGDb
Package 14-ld TSSOP
UV & OV Detection UV pin, OV pin





Description

The ADM1073 is a full-feature, negative voltage, hot swap controller that allows boards to be safely inserted and removed from a live −48 V backplane. The part provides precise and robust current limiting, and protection against both transient and nontransient short circuits in overvoltage and undervoltage conditions. The ADM1073 can operate from a negative voltage of −18 V to −80 V and can tolerate transient voltages of up to −200 V.

Inrush current is limited to a programmable value by controlling the gate drive of an external N-channel FET in ADM1073. The maximum current limit is set by the choice of the sense resistor, RSENSE. A built-in soft start function allows control of the inrush current profile by an external capacitor on the soft start (SS) pin.

An external capacitor on the TIMER pin determines the time for which the FET gate is controlled to be high when maximum inrush current flows. The ADM1073 employs a limited consecutive retry scheme, whereby, if the load capacitance is not fully charged within one attempt, the FET gate is pulled low and retries after a cooling period.






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