ADSP-21266

The ADSP-21266 SHARC DSP is a member of the SIMD SHARC family of DSPs featuring Analog Devices' Super Harvard Architecture. The ADSP-21266 is source code compatible with the ADSP-21160 and ADSP-21161 DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, the ADSP-21266 is a 32-bit processor optimized for high performance audio applications. The ADSP-21266 is available in a 200 MHz or a 150 MHz core, dual-ported on-chip SRAM and mask-programmable ROM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI).

The ADSP-21266 offers a Single-Instruction Multiple-Data (SIMD) architecture, which was first introduced with the ADSP- 21160 and ADSP-21161. As shown in the Functional Block Diagram on page 1, the ADSP-21266 uses two computational units to deliver a 5 to 10 times performance increase over the ADSP-2106x on a range of DSP algorithms. Fabricated in a state-of-the-art, high speed, low power CMOS process, the ADSP-21266 DSP achieves an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at150 MHz. With its SIMD computational hardware, the ADSP-21266 can perform 1200 MFLOPS running at 200 MHz, or 900 MFLOPS running at150 MHz.