ADSP-2186N

The ADSP-218xN series consists of six single chip micro- computers optimized for digital signal processing applica- tions. The high-level block diagram for the ADSP-218xN  series members appears on the previous page. All series  members are pin-compatible and are differentiated solely by  the amount of on-chip SRAM. This feature, combined with  ADSP-21xx code compatibility, provides a great deal of  flexibility in the design decision.

ADSP-218xN series members combine the ADSP-2100  family base architecture (three computational units, data  address generators, and a program sequencer) with two  serial ports, a 16-bit internal DMA port, a byte DMA port,  a programmable timer, Flag I/O, extensive interrupt capa-bilities, and on-chip program and data memory.

ADSP-218xN series members integrate up to 256Kbytes  of on-chip memory configured as up to 48Kwords (24-bit)  of program RAM, and up to 56Kwords (16-bit) of data  RAM. Power-down circuitry is also provided to meet the  low power needs of battery-operated portable equipment.  The ADSP-218xN is available in a 100-lead LQFP package  and 144-Ball Mini-BGA.

Fabricated in a high-speed, low-power, 0.18|ìm CMOS process, ADSP-218xN series members operate with a  12.5ns instruction cycle time. Every instruction can  execute in a single processor cycle.