ADSP-21990

· Industrial Motor Drives
· Un-Interruptible Power Supplies
· Optical Networking Control
· Data Acquisition Systems
· Test and Measurement Systems
· Portable Instrumentation

V_DDINTInternal (Core) Supply Voltage^1,2 . . . . . . 0.3 to 3.0 V
V_DDEXTExternal (I/O) Supply Voltage. . . . . . . . . .0.3 to 4.6 V
V_ILVI_HInput Voltage . . . . . . . . . . . . . .0.5 to VDDEXT+0.5 V
V_OLV_OHOutput Voltage Swing . . . . . . 0.5 to VDDEXT+0.5 V
C_LLoad Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . .  200 pF
t_CCLKCore Clock Period . . . . . . . . . . . . . . . . . . . . . . .  6.25 ns
f_CCLKCore Clock Frequency . . . . . . . . . . . . . . . . . . . . 160 MHz
t_HCLKPeripheral Clock Period . . . . . . . . . . . . . . . . . . . . . 10 ns
f_HCLKPeripheral Clock Frequency . . . . . . . . . . . . . . . . . 80 MHz
T_STOREStorage Temperature Range . . . . . . . . . . 65 to 150
T_LEADLead Temperature (5 seconds) . . . . . . . . . . . . . . . .185

¹Specifications subject to change without notice.

²Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The ADSP-21990 is a mixed signal DSP controller based on the ADSP-219x DSP Core, suitable for a variety of high performance Industrial Motor Control and Signal Processing applications that require the combination of a high performance DSP and the mixed signal integration of embedded control peripherals such as analog to digital conversion.

The ADSP-21990 integrates the 160 MIPS, fixed point ADSP-219x family base architecture with a serial port, an SPI compatible port, a DMA controller, three programmable timers, general purpose Programmable Flag pins, extensive interrupt capabilities, on chip program and data memory spaces, and a complete set of embedded control peripherals that permits fast motor control and signal processing in a highly integrated environment.

The ADSP-21990 architecture is code compatible with previous ADSP-217x based ADMCxxx products. Although the architectures are compatible, the ADSP-21990, with ADSP-219x architecture, has a number of enhancements over earlier architectures. The enhancements to computational units, data address generators, and program sequencer make it more flexible and easier to program than the previous ADSP-21xx embedded DSPs.

Indirect addressing options provide addressing flexibility-premodify with no update, pre- and post-modify by an immediate 8-bit, two's complement value and base address registers for easier implementation of circular buffering.

The ADSP-21990 integrates 8K words of on chip memory configured as 4K words (24-bit) of program RAM, and 4K words (16-bit) of data RAM.

Fabricated in a high speed, low power, CMOS process, the ADSP-21990 operates with a 6.25 ns instruction cycle time (160 MIPS). All instructions, except two multiword instructions, execute in a single DSP cycle.

The ADSP-21990's flexible architecture and comprehensive instruction set support multiple operations in parallel.

For example, in one processor cycle, it can:
• Generate an address for the next instruction fetch
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation These operations take place while the processor continues to:
• Receive and transmit data through the serial port
• Receive or transmit data over the SPI port
• Access external memory through the external memory interface
• Decrement the timers
• Operate the embedded control peripherals (ADC, PWM, EIU, etc.)