MFG:48 Package Cooled:QFP D/C:06+
MFG: 48
Package Cooled: QFP
D/C: 06+
Description: family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin p...
family of products, incorporating the Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
The ADSP-BF531/2/3 processors are completely code and pin compatible, differing only with respect to their performance and on-chip memory. Specific performance and memory configurations are shown in Table 1.
Stresses greater than those listed in the table may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
For proper SDRAM controller operation, the maximum load capacitance is 50 pF (at 3.3 V) or 30 pF (at 2.5 V) for ADDR191, DATA150, ABE10/SDQM10, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, and SMS.
| Parameter | Rating |
| Internal (Core) Supply Voltage (VDDINT) | 0.3 V to +1.4 V |
| External (I/O) Supply Voltage (VDDEXT) | 0.3 V to +3.8 V |
| Input Voltage | 0.5 V to 3.6 V |
| Output Voltage Swing | 0.5 V to VDDEXT+0.5 V |
| Load Capacitance | 200 pF |
| ADSP-BF533 Core Clock (CCLK) | 600 MHz |
| ADSP-BF532/BF531 Core Clock (CCLK) | 400 MHz |
| Peripheral Clock (SCLK) | 133 MHz |
| Storage Temperature Range | 65ºC to +150ºC |
| Junction Temperature Under Bias | 125ºC |
ADSP-BF531
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